Here is the configuration used: There must be something to fix because there are numerous examples of people reaching high transfer rates. That delay between bytes is based on how long it takes the chip to move the next byte from its internal buffer to the output shift registers. In what size chunks? Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of service , privacy policy and cookie policy , and that your continued use of the website is subject to these policies. Sign up using Facebook.

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I’ve tried other length, etc no change. Sign up using Email and Password.

This is what it looked like on my logic analyzer when I output 6 bytes at once at a clock rate of 5MHz. That’s often now understood, but SPI fft232hl involve coordination with other signals like selects, so it’s easy to imagine being ft232hll by bus framing and unable to leverage the theoretical data rate that would apply to larger transfers. By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.

I have it set tobut often for timing sensitive stuff, I have it lower 2 Try a slower clockrate first just to fhdi and make sure the device is communicating correctly I assume you did, I’m just adding this in case someone else hasn’t tried that yet.

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There is is a small delay between bytes, but nowhere near as large as 64us.

tfdi USB peripherals can slow to a crawl if they only get a byte or few moved per frame. Why are you looking only at SPI side of your bridge? That delay between bytes is based on how long it takes the chip to move the next byte from its internal buffer to the output shift registers.

LatencyTimer would help, but it shows no difference no matter the value used 10,rtdi, delay remain 64uS between consecutive bytes. Here is some quick example code on how to send multiple data bytes in case it helps. I have no idea how fast the USB transmit the data. I heard back from FTDI guys, they suggest I don’t use their library but they didn’t clearly say that their lib was bugged.

I’ve ftdo sample code provided with sample-dynamic. As written on the message, no matter how many bytes sent at once, the delay is same. How are you delivering the data to the drivers? I’ve contacted FTDI support, they asked me to update the libraries to latest one which I ftduthen they would not provide further support.

I did check with a logic analyser, the bytes are correctly sent out and the SPI clock match the settings. Note that for SPI it doesn’t matter if the clock is stretched a little bit ttdi and there since it is based on the edges of the clock signal read on one edge, propagate on the other.

There must be something to fix because there are numerous examples of people reaching high transfer rates. If you make a single call, add the appropriate chip select enable and disable flags see below. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated ff232hl of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.

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Are you sure that USB side is sending data fast enough? In what size chunks? Also, I use master fdti mode, write-only, there shouldn’t be any handshaking involved. I imagined maybe playing with the channelConf. Here are some things to check.

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If this is a custom board design, or you bought a discount FTH adapter board, make sure it has the correct system clock frequency. Sign up using Facebook. Also, delay between bytes should be a setting somewhere. Here is the configuration used:.

I’m still surprised some people can reach high transfer speeds out of the box and using the provided lib. Post as a guest Name.

FTDI FTH USB 12Mbps results – Black Mesa Labs

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If the chip is clocked slowly, then this will show at the higher frequencies as a larger gap between bytes. Here is the configuration used: